1. Field of the Invention
The present invention generally relates to relay boards and semiconductor devices having the relay boards, and more specifically, to a relay board used for wiring the semiconductor chips to each other, or the semiconductor chip to and a wiring board or a lead frame, and the semiconductor device having the relay board.
2. Description of the Related Art
A semiconductor device having a structure where at least one semiconductor chip (semiconductor element) and a wiring substrate or a lead frame are connected by a bonding wire is known. In such a semiconductor device, depending on arrangements of electrode pads of the semiconductor chip and bonding pads of the wiring substrate or a bonding lead of the lead frame, crossing or superposing of the bonding wires happens, a length of the bonding wire is too long, or the like so that wire-bonding may be hard to accomplish.
In order to solve such a problem, as shown in FIG. 1, a structure where a relay board for relaying wiring by bonding wires is provided in a semiconductor device has been suggested.
FIG. 1 is a cross-sectional view of a related art semiconductor device having the relay board. Here, FIG. 1-(A) is a cross-sectional view taken along a line X-X′ of FIG. 1-(B) which is a plan view of this related art semiconductor device.
Referring to FIG. 1, a semiconductor device 10 has a structure where a first semiconductor chip 6 is mounted on a wiring board 4 having a lower surface where plural bumps 2 are formed. A second semiconductor chip 8 and a relay board 20 are provided on the first semiconductor chip 6.
A bonding pad 1a of the wiring board 4 is connected to an electrode pad 7 of a first semiconductor chip 6 by a bonding wire 3. A bonding pad 1b of the wiring board 4 is connected to a first electrode pad 11 of the second semiconductor chip 8 by a bonding wire 5. A bonding pad 13 of the second semiconductor chip 8 is connected to a first bonding pad 22 of the relay board 20 by a bonding wire 23. A second bonding pad 24 of the relay board 20 is connected to another bonding pad 1b of the wiring board 4 by a bonding wire 25.
The first bonding pad 22 and the second bonding pad 24 of the relay board 20 faces each other. A wiring 26 connects the first bonding pad 22 and the second bonding pad 24 in a straight line state.
Furthermore, the first semiconductor chip 6, the second semiconductor chip 8, the relay board 20, and the bonding wires 3, 5, 23 and 25 are sealed by sealing resin 9 so that the semiconductor 10 is made packaged.
Thus, the relay board 20 is provided between the second electrode pad 13 of the second semiconductor chip 8 and the bonding pad 1b of the wiring board 4 and the second semiconductor chip 8 and the relay board 20 are wire-bonded so that the second semiconductor chip 8 and the wiring board 4 are electrically connected.
In this case, the second electrode pad 13 of the second semiconductor chip 8 is greatly separated from the bonding pad 1b of the wiring board 4. Hence, if the relay board 20 is not provided, a bonding wire having a long wiring length is necessary. However, because of the wiring board 20, the wiring length can be shortened.
In addition, as shown in FIG. 2 and FIG. 3, a relay board having an arrangement of bonding pads different from the example shown in FIG. 1 has been suggested.
FIG. 2 is a plan view of a related art relay board having an arrangement of bonding pads different from the example shown in FIG. 1.
In the relay board 30 shown in FIG. 2, the arrangement direction of a first bonding pad group 31A through 31F is perpendicular to the arrangement direction of a second bonding pad group 32A through 32F. Pads corresponding to each other of the first bonding pad group 31A through 31F and the second bonding pad group 32A through 32F are connected by wiring 33A through 33F extending in an L-shape.
Hence, this structure is effective in a case where the angle between a connecting direction of a bonding wire from a bonding pad and another connecting direction of another bonding wire from another bonding pad is approximately 90 degrees.
FIG. 3 is a plan view of another related art relay board having an arrangement of bonding pads different from the examples shown in FIG. 1 and FIG. 2.
In the relay board 40 shown in FIG. 3, wirings 43A through 43D for connecting first bonding pads 41A through 41D and second bonding pads 42A through 42D are provided so as to be bent on the way plural times (bent line state). Thus, change of the arrangement of the bonding pads is realized.
That is, the first bonding pads 41A through 41D are provided in the vicinity of and along a side (upper side) of the relay board 40. The second bonding pads 42A through 42D are provided in the vicinity of and along a side (lower side) of the relay board 40.
The first bonding pad 41A and the second bonding pad 42A can be electrically connected by the wiring 43A bent on the way plural times. The first bonding pad 41B and the second bonding pad 42B can be electrically connected by the wiring 43B bent on the way plural times. The first bonding pad 41C and the second bonding pad 42C can be electrically connected by the wiring 43C bent on the way plural times. The first bonding pad 41D and the second bonding pad 42D can be electrically connected by the wiring 43D bent on the way plural times.
Furthermore, in addition to the above-discussed examples, a semiconductor device having a structure where a relay board and a semiconductor chip are arranged to be substantially coplanar and connected by wiring-bonding (See Japan Laid-Open Patent Application Publications No. 2-109344 and No. 2-216839), a semiconductor device having a structure where a relay board smaller than a semiconductor chip is mounted on the semiconductor chip (See Japan Laid-Open Patent Application Publications No. 5-13490 and No. 2004-153295), a semiconductor device having a structure where a relay board is provided under a semiconductor chip (See Japan Laid-Open Patent Application Publication No. 2002-515175), a semiconductor device having a structure where plural semiconductor devices are laminated and a semiconductor chip situated at the top and a relay board are arranged side by side (See Japan Laid-Open Patent Application Publication No. 2001-118877), and a semiconductor device having a structure where a relay board is provided in plural laminated semiconductor chips (See Japan Laid-Open Patent Application Publications No. 11-265975 and No. 2001-7278) are known.
However, the size of the semiconductor chip or the wiring board, and the number and the way of arrangement of electrode pads formed on the semiconductor chip or bonding pads formed on the wiring board vary. Therefore, a relay board suitable for a certain semiconductor device is not always suitable for other semiconductor device.
That is, in the related art relay boards, for every semiconductor device, bonding pads of the relay board are positioned corresponding to the arrangement of the electrode pads of the semiconductor chip or the bonding pads of the wiring board or the lead frame. Hence, depending on a positional relationship of the pads of the semiconductor chip and the wiring board, the relay board 20, 30 or 40 shown in FIG. 1 through FIG. 3 cannot correspond. Therefore, a relay board has to be manufactured corresponding to the positional relationship of the pads of the semiconductor chip and the wiring board. Hence, such a relay board cannot be placed in a wide use.
The way of mounting a semiconductor chip on a semiconductor device, the arrangement of electrode pads of a semiconductor chip, or the connection structure between a semiconductor chip and a wiring board or a lead frame may need to be changed. In addition, for the purpose of improvement of yield in manufacturing existing semiconductor devices, positions of the bonding pads of the relay board may need to be changed. The related art relay boards do not correspond to these structures and it is necessary to newly provide a relay board having a different structure.